Direct Memory Access Cascade

Well...As stated in the top of the thread. I am just wondering how the two controllers of the DMA Cascade are linked. I have done an extensive of research and have read several books, none of which really illustrate and talk about this in details.

According to the book I read, it is said that the first controller is linked to the second controller and this is done through DMA channel 4. But how do both controller get linked isn't mentioned in the book?

Because there are 8 channels of DMA 0 - 3 for controller one, 5 - 7 for controller two. So the question is
Does DMA 4 appear on both of the controller? so DMA 4 of the first controller is linked with the DMA 4 of the second controller?

Or

Does the second controller contain 4 - 7 DMA? But then what channel of the DMA of the first controller is linked to the DMA 4 of the second controller? It is a bit confusing. And I really don't get it.